Espressif Systems /ESP32 /UART0 /INT_RAW

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Interpret as INT_RAW

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RXFIFO_FULL_INT_RAW)RXFIFO_FULL_INT_RAW 0 (TXFIFO_EMPTY_INT_RAW)TXFIFO_EMPTY_INT_RAW 0 (PARITY_ERR_INT_RAW)PARITY_ERR_INT_RAW 0 (FRM_ERR_INT_RAW)FRM_ERR_INT_RAW 0 (RXFIFO_OVF_INT_RAW)RXFIFO_OVF_INT_RAW 0 (DSR_CHG_INT_RAW)DSR_CHG_INT_RAW 0 (CTS_CHG_INT_RAW)CTS_CHG_INT_RAW 0 (BRK_DET_INT_RAW)BRK_DET_INT_RAW 0 (RXFIFO_TOUT_INT_RAW)RXFIFO_TOUT_INT_RAW 0 (SW_XON_INT_RAW)SW_XON_INT_RAW 0 (SW_XOFF_INT_RAW)SW_XOFF_INT_RAW 0 (GLITCH_DET_INT_RAW)GLITCH_DET_INT_RAW 0 (TX_BRK_DONE_INT_RAW)TX_BRK_DONE_INT_RAW 0 (TX_BRK_IDLE_DONE_INT_RAW)TX_BRK_IDLE_DONE_INT_RAW 0 (TX_DONE_INT_RAW)TX_DONE_INT_RAW 0 (RS485_PARITY_ERR_INT_RAW)RS485_PARITY_ERR_INT_RAW 0 (RS485_FRM_ERR_INT_RAW)RS485_FRM_ERR_INT_RAW 0 (RS485_CLASH_INT_RAW)RS485_CLASH_INT_RAW 0 (AT_CMD_CHAR_DET_INT_RAW)AT_CMD_CHAR_DET_INT_RAW

Fields

RXFIFO_FULL_INT_RAW

This interrupt raw bit turns to high level when receiver receives more data than (rx_flow_thrhd_h3 rx_flow_thrhd).

TXFIFO_EMPTY_INT_RAW

This interrupt raw bit turns to high level when the amount of data in transmitter’s fifo is less than ((tx_mem_cnttxfifo_cnt) .

PARITY_ERR_INT_RAW

This interrupt raw bit turns to high level when receiver detects the parity error of data.

FRM_ERR_INT_RAW

This interrupt raw bit turns to high level when receiver detects data’s frame error .

RXFIFO_OVF_INT_RAW

This interrupt raw bit turns to high level when receiver receives more data than the fifo can store.

DSR_CHG_INT_RAW

This interrupt raw bit turns to high level when receiver detects the edge change of dsrn signal.

CTS_CHG_INT_RAW

This interrupt raw bit turns to high level when receiver detects the edge change of ctsn signal.

BRK_DET_INT_RAW

This interrupt raw bit turns to high level when receiver detects the 0 after the stop bit.

RXFIFO_TOUT_INT_RAW

This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.

SW_XON_INT_RAW

This interrupt raw bit turns to high level when receiver receives xoff char with uart_sw_flow_con_en is set to 1.

SW_XOFF_INT_RAW

This interrupt raw bit turns to high level when receiver receives xon char with uart_sw_flow_con_en is set to 1.

GLITCH_DET_INT_RAW

This interrupt raw bit turns to high level when receiver detects the start bit.

TX_BRK_DONE_INT_RAW

This interrupt raw bit turns to high level when transmitter completes sendding 0 after all the datas in transmitter’s fifo are send.

TX_BRK_IDLE_DONE_INT_RAW

This interrupt raw bit turns to high level when transmitter has kept the shortest duration after the last data has been send.

TX_DONE_INT_RAW

This interrupt raw bit turns to high level when transmitter has send all the data in fifo.

RS485_PARITY_ERR_INT_RAW

This interrupt raw bit turns to high level when rs485 detects the parity error.

RS485_FRM_ERR_INT_RAW

This interrupt raw bit turns to high level when rs485 detects the data frame error.

RS485_CLASH_INT_RAW

This interrupt raw bit turns to high level when rs485 detects the clash between transmitter and receiver.

AT_CMD_CHAR_DET_INT_RAW

This interrupt raw bit turns to high level when receiver detects the configured at_cmd chars.

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